Bjt Ac

     CHAPTER  OBJECTIVES 

 ● 

  

● 

  Become familiar with the  r 

e

  , hybrid, and hybrid 

p models for the BJT transistor.  

  

● 

  Learn to use the equivalent model to find the important ac parameters for an amplifier.  

  

● 

  Understand the effects of a source resistance and load resistor on the overall gain and 
characteristics of an amplifier.  

  

● 

  Become aware of the general ac characteristics of a variety of important BJT 
configurations.  

  

● 

  Begin to understand the advantages associated with the two-port systems approach to 
single- and multistage amplifiers.  

  

● 

  Develop some skill in troubleshooting ac amplifier networks.    

      5.1 

 INTRODUCTION 

 ● 

 The basic construction, appearance, and characteristics of the transistor were introduced in 
 Chapter   3   . The dc biasing of the device was then examined in detail in  Chapter   4   . We now 
begin to examine the ac response of the BJT amplifier by reviewing the  models  most fre-
quently used to represent the transistor in the sinusoidal ac domain. 

 One of our first concerns in the sinusoidal ac analysis of transistor networks is the mag-

nitude of the input signal. It will determine whether  small-signal  or  large-signal   techniques 
should be applied. There is no set dividing line between the two, but the application—and 
the magnitude of the variables of interest relative to the scales of the device characteristics—
will usually make it quite clear which method is appropriate. The small-signal technique is 
introduced in this chapter, and large-signal applications are examined in  Chapter   12   . 

 There are three models commonly used in the small-signal ac analysis of transistor 

networks: the  r 

e

   model, the hybrid 

p model, and the hybrid equivalent model. This chapter 

introduces all three but emphasizes the  r 

e

   model.  

   5.2 

 AMPLIFICATION  IN  THE  AC  DOMAIN 

 ● 

 It was demonstrated in  Chapter   3    that the transistor can be employed as an amplifying device. 
That is, the output sinusoidal signal is greater than the input sinusoidal signal, or, stated 
another way, the output ac power is greater than the input ac power. The question then arises 
as to how the ac power output can be greater than the input ac power. Conservation of energy 
dictates that over time the total power output,  P 

o

  , of a system cannot be greater than its power 

    5 

 BJT AC Analysis 

253

input,  P 

i

  , and that the efficiency defined by    

h = P

o

>P

i

    cannot be greater than 1. The factor 

missing from the discussion above that permits an ac power output greater than the input ac 
power is the applied dc power. It is the principal contributor to the total output power even 
though part of it is dissipated by the device and resistive elements. In other words, there is an 
“exchange” of dc power to the ac domain that permits establishing a higher output ac power. 
In fact, a  conversion efficiency  is defined by    

h = P

o(ac)

>P

i(dc)

,     where     P

o(ac)

    is the ac power 

to the load and    P

i(dc)

    is the dc power supplied. 

 Perhaps the role of the dc supply can best be described by first considering the simple 

dc network of  Fig.   5.1   . The resulting direction of flow is indicated in the figure with a plot 
of the current  i  versus time. Let us now insert a control mechanism such as that shown in 
 Fig.   5.2   . The control mechanism is such that the application of a relatively small signal to 
the control mechanism can result in a substantial oscillation in the output circuit. 

  

BJT AC ANALYSIS

254

 

I

dc

I

dc

I

dc

I

dc

I

dc

E

R

i

t

0

+

–

 FIG. 5.1 

          Steady  current  established  by  a 

dc  supply.    

i

T

i

c

i

T

i

T

i

T

R

i

T 

= I

dc 

+ i

ac

t

0

Control
mechanism

E

+

–

 FIG. 5.2 

         Effect of a control element on the steady-state flow of the electrical 

system  of   Fig.    5.1   .    

 That is, for this example, 

 

   i

ac(p

@p)

W i

c(p

@p)

   

 and amplification in the ac domain has been established. The peak-to-peak value of the 
output current far exceeds that of the control current. 

 For the system of  Fig.   5.2   , the peak value of the oscillation in the output circuit is con-

trolled by the established dc level. Any attempt to exceed the limit set by the dc level will 
result in a “clipping” (flattening) of the peak region at the high and low end of the output 
signal. In general, therefore, proper amplification design requires that the dc and ac com-
ponents be sensitive to each other’s requirements and limitations. 

 However, it is extremely helpful to realize that: 

  The superposition theorem is applicable for the analysis and design of the dc and ac 
components of a BJT network, permitting the separation of the analysis of the dc and 
ac responses of the system.  

 In other words, one can make a complete dc analysis of a system before considering the 

ac response. Once the dc analysis is complete, the ac response can be determined using a 
completely ac analysis. It happens, however, that one of the components appearing in the 
ac analysis of BJT networks will be determined by the dc conditions, so there is still an 
important link between the two types of analysis.  

   5.3 

 BJT  TRANSISTOR  MODELING 

 ● 

 The key to transistor small-signal analysis is the use of the equivalent circuits (models) to 
be introduced in this chapter. 

  A model is a combination of circuit elements, properly chosen, that best approximates 
the actual behavior of a semiconductor device under specific operating conditions.  

 Once the ac equivalent circuit is determined, the schematic symbol for the device can 

be replaced by this equivalent circuit and the basic methods of circuit analysis applied to 
determine the desired quantities of the network. 

 In the formative years of transistor network analysis the  hybrid equivalent network   was 

employed the most frequently. Specification sheets included the parameters in their listing, 
and analysis was simply a matter of inserting the equivalent circuit with the listed values. 

The drawback to using this equivalent circuit, however, is that it is  defined for a set of oper-
ating conditions that might not match the actual operating conditions.  In most cases, this is 
not a serious flaw because the actual operating conditions are relatively close to the chosen 
operating conditions on the data sheets. In addition, there is always a variation in actual 
resistor values and given transistor beta values, so as an approximate approach it was quite 
reliable. Manufacturers continue to specify the hybrid parameter values for a particular 
operating point on their specification sheets. They really have no choice. They want to give 
the user some idea of the value of each important parameter so comparisons can be made 
between transistors, but they really do not know the user’s actual operating conditions. 

 In time the use of the  r 

e

   model  became the more desirable approach because an impor-

tant parameter of the equivalent circuit was determined by the actual operating conditions 
rather than using a data sheet value that in some cases could be quite different. Unfortu-
nately, however, one must still turn to the data sheets for some of the other parameters of 
the equivalent circuit. The  r 

e

   model also failed to include a feedback term, which in some 

cases can be important if not simply troublesome. 

 The   r 

e

   model is really a reduced version of the  hybrid  

p  model  used almost exclusively 

for high-frequency analysis. This model also includes a connection between output and 
input to include the feedback effect of the output voltage and the input quantities. The full 
hybrid model is introduced in  Chapter    9   . 

 Throughout the text the  r 

e

   model is the model of choice unless the discussion centers 

on the description of each model or a region of examination that predetermines the model 
that should be used. Whenever possible, however, a comparison between models will be 
discussed to show how closely related they really are. It is also important that once you gain 
a proficiency with one model it will carry over to an investigation using a different model, 
so moving from one to another will not be a dramatic undertaking. 

 In an effort to demonstrate the effect that the ac equivalent circuit will have on the 

analysis to follow, consider the circuit of  Fig.   5.3   . Let us assume for the moment that the 
small-signal ac equivalent circuit for the transistor has already been determined. Because 
we are interested only in the ac response of the circuit, all the dc supplies can be replaced 
by a zero-potential equivalent (short circuit) because they determine only the dc (quiescent 
level) of the output voltage and not the magnitude of the swing of the ac output. This is 
clearly demonstrated by  Fig.   5.4   . The dc levels were simply important for determining the 
proper  Q -point of operation. Once determined, the dc levels can be ignored in the ac analy-
sis of the network. In addition, the coupling capacitors  C  

1

  and  C  

2

  and bypass capacitor  C  

3

  

were chosen to have a very small reactance at the frequency of application. Therefore, they, 
too, may for all practical purposes be replaced by a low-resistance path or a short circuit. 
Note that this will result in the “shorting out” of the dc biasing resistor  R 

E

  . Recall that ca-

pacitors assume an “open-circuit” equivalent under dc steady-state conditions, permitting 
an isolation between stages for the dc levels and quiescent conditions. 

  

255

BJT TRANSISTOR 

MODELING

 FIG. 5.3 

          Transistor  circuit  under  examination  in  this  introductory  discussion.    

BJT AC ANALYSIS

256

 

 It is important as you progress through the modifications of the network to define the ac 

equivalent that the parameters of interest such as    Z

i

, Z

o

, I

i

,     and   I 

o

   as  defined  by   Fig.    5.5     be 

carried through properly. Even though the network appearance may change, you want to be 
sure the quantities you find in the reduced network are the same as defined by the original 
network. In both networks the input impedance is defined from base to ground, the input 
current as the base current of the transistor, the output voltage as the voltage from collector 
to ground, and the output current as the current through the load resistor  R 

C

  . 

I

i

I

o

Z

i

Z

o

V

o

V

i

+

+

–

–

 FIG. 5.4 

          The  network  of   Fig.    5.3     following  removal  of  the  dc 

supply and insertion of the short-circuit equivalent 

for the capacitors.    

I

i

Z

i

+

I

o

Z

o

V

i

V

o

+

–

–

System

 FIG. 5.5 

          Defining  the  important  parameters 

of any system.    

I

i

I

o

V

i

V

o

+

–

+

–

+

–

+

–

R

i

R

o

 FIG. 5.6 

          Demonstrating  the  reason  for  the  defined 

directions and polarities.    

 The parameters of  Fig.   5.5    can be applied to any system whether it has one or a thou-

sand components. For all the analysis to follow in this text, the directions of the currents, 
the polarities of the voltages, and the direction of interest for the impedance levels are as 
appearing in  Fig.   5.5   . In other words, the input current  I 

i

   and output current  I 

o

   are, by defini-

tion, defined to enter the system. If, in a particular example, the output current is leaving the 
system rather than entering the system as shown in  Fig.   5.5   , a minus sign must be applied. 
The defined polarities for the input and output voltages are also as appearing in  Fig.   5.5   . If 
 V 

o

   has the opposite polarity, the minus sign must be applied. Note that  Z 

i

   is the impedance 

“looking into” the system, whereas  Z 

o

   is the impedance “looking back into” the system 

from the output side. By choosing the defined directions for the currents and voltages as 
appearing in  Fig.   5.5   , both the input impedance and output impedance are defined as having 
positive values. For example, in  Fig.   5.6    the input and output impedances for a particular 
system are both resistive. For the direction of  I 

i

   and  I 

o

   the resulting voltage across the resis-

tive elements will have the same polarity as  V 

i

   and  V 

o

  , respectively. If  I 

o

   had been defined 

as the opposite direction in  Fig.   5.5    a minus sign would have to be applied. For each case 
   Z

i

= V

i

>I

i

     and     Z

o

= V

o

>I

o

    with positive results if they all have the defined directions and 

polarity of  Fig.   5.5   . If the output current of an actual system has a direction opposite to that 

257

THE  r

e

 TRANSISTOR 

MODEL

of  Fig.   5.5    a minus sign must be applied to the result because  V 

o

   must be defined as appear-

ing in  Fig.   5.5   . Keep  Fig.   5.5    in mind as you analyze the BJT networks in this chapter. It is 
an important introduction to “System Analysis,” which is becoming so important with the 
expanded use of packaged IC systems. 

  

 If we establish a common ground and rearrange the elements of  Fig.   5.4   ,  R  

1

  and  R  

2

   will 

be in parallel, and  R 

C

   will appear from collector to emitter as shown in  Fig.   5.7   . Because 

the components of the transistor equivalent circuit appearing in  Fig.   5.7    employ familiar 
components such as resistors and independent controlled sources, analysis techniques 
such as superposition, Thévenin’s theorem, and so on, can be applied to determine the 
desired quantities. 

B

I

i

Z

i

 FIG. 5.7 

          Circuit  of   Fig.    5.4     redrawn  for  small-signal  ac  analysis.    

+

–

V

i

+

–

V

be

B

C

E

I

e

I

b

 FIG. 5.8 

          Finding  the  input  equivalent  circuit 

for a BJT transistor.    

 Let us further examine  Fig.   5.7    and identify the important quantities to be determined 

for the system. Because we know that the transistor is an amplifying device, we would 
expect some indication of how the output voltage  V 

o

   is related to the input voltage  V 

i

  —

the  voltage gain.  Note in  Fig.   5.7    for this configuration that the  current gain  is defined 
by     A

i

= I

o

>I

i

.    

 In summary, therefore, the ac equivalent of a transistor network is obtained by: 

    1.    Setting all dc sources to zero and replacing them by a short-circuit equivalent  
   2.    Replacing all capacitors by a short-circuit equivalent  
   3.    Removing all elements bypassed by the short-circuit equivalents introduced by steps 

1 and 2  

   4.    Redrawing the network in a more convenient and logical form   

 In the sections to follow, a transistor equivalent model will be introduced to complete 

the ac analysis of the network of  Fig.    5.7   . 

 

 

   5.4 

 THE   r 

e

   TRANSISTOR MODEL 

 ● 

 The   r 

e

   model for the CE, CB, and CC BJT transistor configurations will now be introduced 

with a short description of why each is a good approximation to the actual behavior of a 
BJT transistor. 

  Common-Emitter  Configuration 

 The equivalent circuit for the common-emitter configuration will be constructed using the 
device characteristics and a number of approximations. Starting with the input side, we find 
the applied voltage  V 

i

   is equal to the voltage  V 

be

   with the input current being the base cur-

rent  I 

b

   as  shown  in   Fig.    5.8   . 

 Recall from  Chapter   3    that because the current through the forward-biased junction of 

the transistor is  I 

E

  , the characteristics for the input side appear as shown in  Fig.   5.9a    for 

various levels of  V 

BE

  . Taking the average value for the curves of  Fig.   5.9a    will result in the 

single curve of  Fig.   5.9b   , which is simply that of a forward-biased diode. 

  

BJT AC ANALYSIS

258

 

 For the equivalent circuit, therefore, the input side is simply a single diode with a current 

 I 

e

  , as shown in  Fig.   5.10   . However, we must now add a component to the network that will 

establish the current  I 

e

   of   Fig.    5.10     using  the  output  characteristics. 

 If we redraw the collector characteristics to have a constant 

b  as  shown  in   Fig.    5.11    

(another approximation), the entire characteristics at the output section can be replaced by 
a controlled source whose magnitude is beta times the base current as shown in  Fig.   5.11   . 
Because all the input and output parameters of the original configuration are now present, the 
equivalent network for the common-emitter configuration has been established in  Fig.   5.12   . 

   

0

0.7 V

(a)

(b)

I

E

V

BE

Various

values
of V

CB

Average

value

of V

CB

0

0.7 V

I

E

V

BE

 FIG. 5.9 

          Defining  the  average  curve  for  the  characteristics  of   Fig.    5.9a   .    

V

be

+

–

I

b

I

e

I

c

 FIG. 5.10 

          Equivalent  circuit  for  the  input  side 

of a BJT transistor.    

I

B1

V

CE

0

I

B2

I

B3

I

B4

I

B5

I

B6

Constant 

β

I

C

 FIG. 5.11 

          Constant  

b   characteristics.    

V

be

V

ce

+

+

–

–

I

b

I

c

I

b

I

e

β

 FIG. 5.12 

          BJT  equivalent  circuit.    

 The equivalent model of  Fig.   5.12    can be awkward to work with due to the direct con-

nection between input and output networks. It can be improved by first replacing the diode 
by its equivalent resistance as determined by the level of  I 

E

  ,  as  shown  in   Fig.    5.13   .  Recall 

from  Section   1.8    that the diode resistance is determined by    r

D

= 26 mV>I

D

.     Using  the  sub-

script  e  because the determining current is the emitter current will result in    r

e

= 26 mV>I

E

.    

 Now, for the input side:  

   Z

i

=

V

i

I

b

=

V

be

I

b

    

 Solving  for     V

be

:     

   V

be

= I

e

r

e

= (I

c

+ I

b

)r

e

= (bI

b

+ I

b

)r

e

       

 

 

= (b + 1)I

b

r

e

    

 and  

   Z

i

=

V

be

I

b

=

(

b + 1)I

b

r

e

I

b

   

 

   Z

i

= (b + 1)r

e

⬵ br

e

  

(5.1)

    

V

i

+

V

be

+

–

–

Z

i

r

e

I

b

β

I

e

I

b

 FIG. 5.13 

          Defining  the  level  of  Z 

i

 .    

259

THE  r

e

 TRANSISTOR 

MODEL

 The result is that the impedance seen “looking into” the base of the network is a resistor 
equal to beta times the value of  r 

e

  , as shown in  Fig.   5.14   . The collector output current is 

still linked to the input current by beta as shown in the same figure. 

r

e

β

I

b

I

c

β

I

b

b

e

c

e

 FIG. 5.14 

          Improved  BJT  equivalent  circuit.    

0

V

CEQ

V

A

V

A 

+ V

CEQ

V

CE  

(V)

Slope = 

1

ro

2

Slope = 

1

ro

1

ΔI

C

ΔI

C

ΔV

CE

ΔV

CE

I

C

(mA)

I

CQ

 FIG. 5.15 

         Defining the Early voltage and the output impedance of a transistor.    

 The equivalent circuit has therefore been defined for the ideal characteristics of  Fig.   5.11   , 

but now the input and output circuits are isolated and only linked by the controlled source—a 
form much easier to work with when analyzing networks. 

  

 

  Early  Voltage 

 We now have a good representation for the input circuit, but aside from the collector out-
put current being defined by the level of beta and  I 

B

  , we do not have a good representation 

for the output impedance of the device. In reality the characteristics do not have the ideal 
appearance of  Fig.   5.11   . Rather, they have a slope as shown In  Fig.   5.15    that defines the 
output impedance of the device. The steeper the slope, the less the output impedance and 
the less ideal the transistor. In general, it is desirable to have large output impedances to 
avoid loading down the next stage of a design. If the slope of the curves is extended until 
they reach the horizontal axis, it is interesting to note in  Fig.   5.15    that they will all intersect 
at a voltage called the Early voltage. This intersection was first discovered by James M. 
Early in 1952. As the base current increases the slope of the line increases, resulting in an 
increase in output impedance with increase in base and collector current. For a particular 
collector and base current as shown in  Fig.   5.15   , the output impedance can be found using 
the following equation: 

 

 

   r

o

=

V

I

=

V

A

+ V

CE

Q

I

C

Q

  

(5.2)    

BJT AC ANALYSIS

260

 

 Typically, however, the Early voltage is sufficiently large compared with the applied 
collector-to-emitter voltage to permit the following approximation. 

 

   r

o

⬵

V

A

I

C

Q

  

(5.3)    

 Clearly, since  V 

A

   is a fixed voltage, the larger the collector current, the less the output 

impedance. 

 For situations where the Early voltage is not available the output impedance can be found 

from the characteristics at any base or collector current using the following equation: 

 

   Slope

=

⌬y
⌬x

=

⌬I

C

⌬V

CE

=

1

r

o

   

 and  

   r

o

=

⌬V

CE

⌬I

C

  

(5.4)    

 For the same change in voltage in  Fig.   5.15    the resulting change in current 

¢ I 

C

   is signifi-

cantly less for    r

o

2

     than     r

o

1

,     resulting  in     r

o

2

    being much larger than    r

o

1

.    

 In situations where the specification sheets of a transistor do not include the Early volt-

age or the output characteristics, the output impedance can be determined from the hybrid 
parameter  h 

oe

   that is normally plotted on every specification sheet. It is a quantity that will 

be described in detail in  Section    5.19   . 

 In any event, an output impedance can now be defined that will appear as a resistor in 

parallel with the output as shown in the equivalent circuit of  Fig.    5.16   . 

 

 FIG. 5.16 

         r 

e

  model for the common-emitter transistor configuration 

including effects of r 

o

 .    

 The equivalent circuit of  Fig.   5.16    will be used throughout the analysis to follow for the 

common-emitter configuration. Typical values of beta run from 50 to 200, with values of 
b r 

e

   typically running from a few hundred ohms to a maximum of 6 k

⍀ to 7 k⍀. The output 

resistance  r  is typically in the range of    40 k

⍀ to 50 k⍀.     

  Common-Base  Configuration 

 The common-base equivalent circuit will be developed in much the same manner as 
applied to the common-emitter configuration. The general characteristics of the input and 
output circuit will generate an equivalent circuit that will approximate the actual behavior 
of the device. Recall for the common-emitter configuration the use of a diode to represent 
the connection from base to emitter. For the common-base configuration of  Fig.   5.17a    the 
 pnp  transistor employed will present the same possibility at the input circuit. The result is 
the use of a diode in the equivalent circuit as shown in  Fig.   5.17b   . For the output circuit, if 
we return to  Chapter   3    and review  Fig.   3.8   , we find that the collector current is related to 
the emitter current by alpha 

a. In this case, however, the controlled source defining the 

collector current as inserted in  Fig.   5.17b    is opposite in direction to that of the controlled 
source of the common-emitter configuration. The direction of the collector current in the 
output circuit is now opposite that of the defined output current. 

 

 For the ac response, the diode can be replaced by its equivalent ac resistance determined 

by     r

e

= 26 mV>I

E

    as shown in  Fig.   5.18   . Take note of the fact that the emitter current 

continues to determine the equivalent resistance. An additional output resistance can be 
determined from the characteristics of  Fig.   5.19    in much the same manner as applied to the 
common-emitter configuration. The almost horizontal lines clearly reveal that the output 
resistance  r 

o

   as appearing in  Fig.   5.18    will be quite high and certainly much higher than that 

for the typical common-emitter configuration. 

 The network of  Fig.   5.18    is therefore an excellent equivalent circuit for the analysis of 

most common-base configurations. It is similar in many ways to that of the common-emitter 
configuration. In general, common-base configurations have very low input impedance 
because it is essentially simply  r 

e

  . Typical values extend from a few ohms to perhaps 50 

. 

The output impedance  r 

o

   will typically extend into the megohm range. Because the output 

current is opposite to the defined  I 

o

   direction, you will find in the analysis to follow that 

there is no phase shift between the input and output voltages. For the common-emitter 
configuration there is a 180 °  phase shift. 

  

 

(a)                                                                                                            (b) 

V

i

+

−

V

o

+

−

Z

o

Z

i

Z

i

Z

o

I

i

I

e

I

c

I

o

I

c

I

o

I

i

I

e

 FIG. 5.17 

         (a) Common-base BJT transistor; (b) equivalent circuit for configuration of (a).    

261

I

i

Z

i

Z

o

r

o

I

e

I

c

V

o

+

–

V

i

+

–

I

o

 FIG. 5.18 

          Common  base  r 

e

   equivalent  circuit.    

0

1

2

3

4

I

C

(mA)

V

CB

Slope = 

1

ro

I

E

 = 4 mA

I

E

 = 3 mA

I

E

 = 2 mA

I

E

 = 1 mA

I

E

 = 0 mA

 FIG. 5.19 

          Defining  Z 

o

 .    

BJT AC ANALYSIS

262

 

  Common-Collector  Configuration 

 For the common-collector configuration, the model defined for the common-emitter configu-
ration of  Fig.   5.16    is normally applied rather than defining a model for the common-collector 
configuration. In subsequent chapters, a number of common-collector configurations will be 
investigated, and the effect of using the same model will become quite apparent.  

  npn versus pnp 

 The dc analysis of npn and pnp configurations is quite different in the sense that the currents 
will have opposite directions and the voltages opposite polarities. However, for an ac analy-
sis where the signal will progress between positive and negative values, the ac equivalent 
circuit will be the same.   

   5.5 

 COMMON-EMITTER  FIXED-BIAS 
CONFIGURATION 

 ● 

 The transistor models just introduced will now be used to perform a small-signal ac analy-
sis of a number of standard transistor network configurations. The networks analyzed rep-
resent the majority of those appearing in practice. Modifications of the standard 
configurations will be relatively easy to examine once the content of this chapter is reviewed 
and understood. For each configuration, the effect of an output impedance is examined for 
completeness. 

 The computer analysis section includes a brief description of the transistor model em-

ployed in the PSpice and Multisim software packages. It demonstrates the range and depth 
of the available computer analysis systems and how relatively easy it is to enter a complex 
network and print out the desired results. The first configuration to be analyzed in detail is 
the common-emitter  fixed-bias  network of  Fig.   5.20   . Note that the input signal  V 

i

   is applied 

to the base of the transistor, whereas the output  V 

o

   is off the collector. In addition, recognize 

that the input current  I 

i

   is not the base current, but the source current, and the output current 

 I 

o

   is the collector current. The small-signal ac analysis begins by removing the dc effects 

of  V 

CC

   and replacing the dc blocking capacitors  C  

1

  and  C  

2

  by short-circuit equivalents, 

resulting in the network of  Fig.    5.21   . 

R

B

R

C

V

o  

V

CC

C

2  

I

o  

Z

o  

Z

i  

C

1  

V

i  

I

i  

B

C

E

 FIG. 5.20 

          Common-emitter  fixed-bias  configuration.    

V

o  

I

i

I

o  

R

C  

R

B 

B

C

E

Z

o  

Z

i  

V

i  

 FIG. 5.21 

          Network  of   Fig.    5.20     following  the  removal 

of the effects of V 

CC

 ,  C 

1

 , and C 

2

 .    

 Note in  Fig.   5.21    that the common ground of the dc supply and the transistor emitter 

terminal permits the relocation of  R 

B

   and  R 

C

   in parallel with the input and output sections 

of the transistor, respectively. In addition, note the placement of the important network 
parameters  Z 

i

  ,   Z 

o

  ,   I 

i

  , and  I 

o

   on the redrawn network. Substituting the  r 

e

   model for the 

common-emitter configuration of  Fig.    5.21     results  in  the  network  of   Fig.    5.22   . 

   

 The next step is to determine 

b,  r 

e

  , and  r 

o

  . The magnitude of 

b is typically obtained 

from a specification sheet or by direct measurement using a curve tracer or transistor 

263

COMMON-EMITTER 

FIXED-BIAS  

CONFIGURATION

testing instrument. The value of  r 

e

   must be determined from a dc analysis of the system, 

and the magnitude of  r 

o

   is typically obtained from the specification sheet or characteristics. 

Assuming that 

b,  r 

e

  , and  r 

o

   have been determined will result in the following equations for 

the important two-port characteristics of the system. 

      

Z 

i

   

 Figure    5.22     clearly  shows  that  

  

 

   Z

i

= R

B

7

br

e

 

  

ohms  

(5.5)

    

 For the majority of situations  R 

B

   is greater than 

b r 

e

   by more than a factor of 10 (recall 

from the analysis of parallel elements that the total resistance of two parallel resistors is 
always less than the smallest and very close to the smallest if one is much larger than the 
other), permitting the following approximation: 

 

   Z

i

 

⬵

 

br

e  

  RB Ú 10br

e

 

   

ohms  

(5.6)     

  

Z 

o

     

  Recall that the output impedance of any system is defined as the impedance  Z 

o

   

determined when  V 

i

  

  0.  For   Fig.    5.22   ,  when   V 

i

  

  0,     I

i

= I

b

= 0,    resulting in an open-

circuit equivalence for the current source. The result is the configuration of  Fig.   5.23   . 
We have 

 

   Z

o

= R

C

7

r

o

 

  

ohms  

(5.7)

    

 If     r

o

Ú 10R

C

,     the  approximation     R

C

7

r

o

⬵ R

C

    is frequently applied, and 

 

   Z

o

⬵ R

C  

  ro Ú 10R

C

  

(5.8)

    

 

 

  

A 

v

     

  The  resistors   r 

o

   and  R 

C

   are in parallel, and 

 

   V

o

= -bI

b

(R

C

7

r

o

)   

 but  

   I

b

=

V

i

br

e

   

 so  that  

   V

o

= -ba

V

i

br

e

b(R

C

7

r

o

)   

 and  

   A

v

=

V

o

V

i

= -

(R

C

7 r

o

)

r

e

  

(5.9)    

 If     r

o

Ú 10R

C

,    so that the effect of  r 

o

   can be ignored, 

 

   A

v

= -

R

C

r

e

  

r

o

Ú10R

C

  

(5.10)    

 Note the explicit absence of 

b in Eqs. (5.9) and (5.10), although we recognize that b must 

be utilized to determine  r 

e

  .  

+

I

b

I

c

b

c

–

+

–

I

b

β  

I

i

I

o  

V

o  

Z

o  

R

C  

R

B 

Z

i  

V

i  

r

e

β

r

o  

 FIG. 5.22 

          Substituting  the  r 

e

   model  into  the  network  of   Fig.    5.21   .    

Z

o  

R

C  

r

o  

 FIG. 5.23 

          Determining  Z 

o

  for the network 

of   Fig.    5.22   .    

BJT AC ANALYSIS

264

 

  

Phase Relationship    

  The negative sign in the resulting equation for  A 

v

   reveals that a 180° 

phase shift occurs between the input and output signals, as shown in  Fig.   5.24   . The is a 
result of the fact that 

b I 

b

   establishes a current through  R 

C

   that will result in a voltage across 

 R 

C

  , the opposite of that defined by  V 

o

  . 

 

V

i

R

C  

V

CC

R

B

V

i  

V

o  

V

o  

t

t

0

0

 FIG. 5.24 

          Demonstrating  the   180°   phase  shift  between  input  and  output  waveforms.    

12 V

I

o

Z

i  

V

i  

I

i  

Z

o  

3 k

Ω

10    F

= 100

β

470 k

Ω

V

o  

= 50 kΩ

r

o

μ 

10    F

μ 

 FIG. 5.25 

           Example    5.1   .    

  

Solution:  

 

 

     a.    DC  analysis: 

 

    I

B

=

V

CC

- V

BE

R

B

=

12 V

- 0.7 V

470 k

= 24.04 mA

 

 I

E

= (b + 1)I

B

= (101)(24.04 mA) = 2.428 mA

 

 r

e

=

26 mV

I

E

=

26 mV

2.428 mA

= 10.71 ⍀

    

   b.        

br

e

= (100)(10.71 ) = 1.071 k

    

         Z

i

= R

B

7

br

e

= 470 k

7

1.071 k

 = 1.07 k⍀    

   c.       Z

o

= R

C

= 3 k⍀     

   d.       A

v

= -

R

C

r

e

= -

3 k

10.71 

= ⴚ280.11     

  

EXAMPLE 5.1 

  For  the  network  of   Fig.    5.25   : 

     a.    Determine   r 

e

  .  

    b.    Find   Z 

i

   (with     r

o

=  ).     

    c.    Calculate   Z 

o

   (with     r

o

=  ).     

    d.    Determine   A 

v

   (with     r

o

=  ).     

   e.    Repeat parts (c) and (d) including    r

o

= 50 k    in all calculations and compare results.   

 

265

VOLTAGE-DIVIDER BIAS

   e.        Z

o

= r

o

7

R

C

= 50 k

7

3 k

 = 2.83 k⍀ vs. 3 k     

        A

v

= -

r

o

7 R

C

r

e

=

2.83 k

10.71 

= ⴚ264.24 vs. -280.11          

   5.6 

 VOLTAGE-DIVIDER  BIAS 

 ● 

 The next configuration to be analyzed is the  voltage-divider   bias  network  of   Fig.    5.26   . 
Recall that the name of the configuration is a result of the voltage-divider bias at the input 
side to determine the dc level of  V 

B

  . 

 Substituting the  r 

e

   equivalent circuit results in the network of  Fig.   5.27   . Note the absence 

of  R 

E

   due to the low-impedance shorting effect of the bypass capacitor,  C 

E

  . That is, at the 

frequency (or frequencies) of operation, the reactance of the capacitor is so small compared 
to  R 

E

   that it is treated as a short circuit across  R 

E

  . When  V 

CC

   is set to zero, it places one 

end of  R  

1

  and  R 

C

   at ground potential as shown in  Fig.   5.27   . In addition, note that  R  

1

   and 

 R  

2

  remain part of the input circuit, whereas  R 

C

   is part of the output circuit. The parallel 

combination of  R  

1

  and  R  

2

  is defined by 

 

   R

 = R

1

7

R

2

=

R

1

R

2

R

1

+ R

2

  

(5.11)    

     

Z 

i

     

  From   Fig.    5.27    

 

   Z

i

= R

7

br

e

  

(5.12)

    

  

 

V

CC

C

1  

C

E  

V

i

I

o  

I

i  

R

C  

C

2  

Z

o 

R

E

R

2

Z

i

B

C

E

R

1

V

o  

 FIG. 5.26 

          Voltage-divider  bias  configuration.    

I

b

β  

I

b 

I

o  

R'

I

i  

+

–

+

–

b

c

e

e

V

o  

R

C  

r

o  

r

e

β

R

2

R

1

V

i

Z

i

Z

o  

 FIG. 5.27 

          Substituting  the  r 

e

  equivalent circuit into the ac equivalent network of  Fig.   5.26   .    

BJT AC ANALYSIS

266

 

  

Z 

o

     

  From   Fig.    5.27     with   V 

i

   set to 0 V, resulting in    I

b

= 0 mA     and     bI

b

= 0 mA,    

 

   Z

o

= R

C

7

r

o

  

(5.13)    

 If     r

o

Ú 10R

C

,    

 

   Z

o

⬵ R

C  

  ro Ú 10R

C

  

(5.14)

     

  

A 

v

     

  Because   R 

C

   and  r 

o

   are in parallel, 

 

   V

o

= -(bI

b

)(R

C

7

r

o

)   

 and  

   I

b

=

V

i

br

e

   

 so  that  

   V

o

= -ba

V

i

br

e

b(R

C

7

r

o

)   

 and  

   A

v

=

V

o

V

i

=

-R

C

7 r

o

r

e

  

(5.15)

    

 which you will note is an exact duplicate of the equation obtained for the fixed-bias con-
figuration. 

 For     r

o

Ú 10R

C

,    

 

   A

v

=

V

o

V

i

⬵ -

R

C

r

e

  

 

r

o

Ú10R

C

  

(5.16)     

  

Phase Relationship    

  The negative sign of Eq. (5.15) reveals a 180° phase shift between 

 V 

o

   and  V 

i

  . 

  

EXAMPLE 5.2 

  For  the  network  of   Fig.    5.28   ,  determine: 

    a.     r 

e

  .  

   b.     Z 

i

  .  

   c.     Z 

o

      (r

o

=  ).     

   d.       A

v

 (r

o

=  ).     

   e.    The parameters of parts (b) through (d) if    r

o

= 50 k     and  compare  results.   

 

Z

o 

V

i

= 90

β

22 V

6.8 k

Ω

10    F

1.5 k

Ω

8.2 k

Ω

56 k

Ω

Z

i  

I

i  

I

o  

V

o  

μ

10    F

μ 

20    F

μ 

 FIG. 5.28 

         Example    5.2   .    

267

CE EMITTER-BIAS 

CONFIGURATION

  

Solution:  

 

 

     a.    DC:  Testing     

bR

E

7 10R

2

,    

 

    (90)(1.5 k

) 7 10(8.2 k)

  

135 k

 7 82 k (satisfied)   

     Using the approximate approach, we obtain 

 

    V

B

=

R

2

R

1

+ R

2

 V

CC

=

(8.2 k

)(22 V)

56 k

 + 8.2 k

= 2.81 V

 

 V

E

= V

B

- V

BE

= 2.81 V - 0.7 V = 2.11 V

 

 I

E

=

V

E

R

E

=

2.11 V

1.5 k

= 1.41 mA

 

 r

e

=

26 mV

I

E

=

26 mV

1.41 mA

= 18.44 ⍀

    

   b.        R

 = R

1

7

R

2

= (56 k)

7

(8.2 k

) = 7.15 k

    

        Z

i

= R

7

br

e

= 7.15 k

7

(90)(18.44 

) = 7.15 k

7

1.66 k

   

 

= 1.35 k⍀

    

   c.       Z

o

= R

C

= 6.8 k⍀     

   d.       A

v

= -

R

C

r

e

= -

6.8 k

18.44 

= ⴚ368.76     

   e.        Z

i

= 1.35 k⍀

    

        Z

o

= R

C

7

r

o

= 6.8 k

7

50 k

 = 5.98 k⍀ vs. 6.8 k

     A

v

= -

R

C

7 r

o

r

e

= -

5.98 k

18.44 

= ⴚ324.3 vs. -368.76     

 There was a measurable difference in the results for  Z 

o

   and  A 

v

  , because the condition 

   r

o

Ú 10R

C

     was   not   satisfied.      

   5.7 

 CE  EMITTER-BIAS  CONFIGURATION 

 ● 

 The networks examined in this section include an emitter resistor that may or may not be 
bypassed in the ac domain. We first consider the unbypassed situation and then modify the 
resulting equations for the bypassed configuration. 

  Unbypassed 

 The most fundamental of unbypassed configurations appears in  Fig.   5.29   . The  r 

e

   equiva-

lent model is substituted in  Fig.   5.30   , but note the absence of the resistance  r 

o

  . The effect 

of  r 

o

   is to make the analysis a great deal more complicated, and considering the fact that in 

R

E

R

B

V

i

Z

i  

I

i  

V

CC

C

2  

Z

o  

C

1

I

o  

V

o  

R

C

 FIG. 5.29 

        CE  emitter-bias  configuration.    

I

b

β  

r

e

β

Z

i

Z

o  

R

E

R

B

R

C

Z

b 

b

c

I

o  

+

–

V

o  

β

(   

+ 1)

I

e 

=

 I

b 

e

+

–

V

i  

I

b 

I

i  

 FIG. 5.30 

        Substituting  the  r 

e

  equivalent circuit into the ac equivalent network of  Fig.   5.29   .    

BJT AC ANALYSIS

268

 

most situations its effect can be ignored, it will not be included in the present analysis. 
However, the effect of  r 

o

   will be discussed later in this section.    

 Applying Kirchhoff’s voltage law to the input side of  Fig.   5.30    results in 

 

    V

i

= I

b

br

e

+ I

e

R

E

   

 or  

    V

i

= I

b

br

e

+ (b + I)I

b

R

E

   

 and the input impedance looking into the network to the right of  R 

B

   is 

 

   Z

b

=

V

i

I

b

= br

e

+ (b + 1)R

E

   

 The result as displayed in  Fig.   5.31    reveals that the input impedance of a transistor with 

an unbypassed resistor  R 

E

   is determined by 

 

   Z

b

= br

e

+ (b + 1)R

E

  

(5.17)    

 Because 

b is normally much greater than 1, the approximate equation is 

 

   Z

b

⬵ br

e

+ bR

E

   

 and  

   Z

b

⬵ b(r

e

+ R

E

)  

(5.18)    

 Because   R 

E

   is usually greater than  r 

e

  , Eq. (5.18) can be further reduced to 

 

   Z

b

⬵ bR

E

  

(5.19)

    

  

Z 

i

     

  Returning  to   Fig.    5.30   ,  we  have 

 

   Z

i

= R

B

7

Z

b

  

(5.20)

     

  

Z 

o

     

  With   V 

i

   set to zero,    I

b

= 0,     and     bI

b

    can be replaced by an open-circuit equivalent. 

The result is 

 

   Z

o

= R

C

  

(5.21)     

  

A 

v

     

 

 

    I

b

=

V

i

Z

b

   

 and  

    V

o

= -I

o

R

C

= -bI

b

R

C

 

 

= -ba

V

i

Z

b

bR

C

   

 with  

   A

v

=

V

o

V

i

= -

bR

C

Z

b

  

(5.22)    

 Substituting     Z

b

⬵ b(r

e

+ R

E

)     gives 

 

   A

v

=

V

o

V

i

⬵ -

R

C

r

e

+ R

E

  

(5.23)    

 and for the approximation    Z

b

⬵ bR

E

,    

 

   A

v

=

V

o

V

i

⬵ -

R

C

R

E

  

(5.24)    

 Note the absence of 

b from the equation for  A 

v

   demonstrating an independence in variation 

of 

b.  

  

Phase Relationship    

  The negative sign in Eq. (5.22) again reveals a 180° phase shift 

between  V 

o

   and  V 

i

  .  

R

E

Z

b

r

e

β

 FIG. 5.31 

          Defining  the  input  impedance  of  a 

transistor with an unbypassed 

 emitter  resistor.    

269

CE EMITTER-BIAS 

CONFIGURATION

  

Effect of  r 

o

 

     

  The equations appearing below will clearly reveal the additional complexity 

resulting from including  r 

o

   in the analysis. Note in each case, however, that when certain 

conditions are met, the equations return to the form just derived. The derivation of each 
equation is beyond the needs of this text and is left as an exercise for the reader. Each 
equation can be derived through  careful  application of the basic laws of circuit analysis 
such as Kirchhoff’s voltage and current laws, source conversions, Thévenin’s theorem, 
and so on. The equations were included to remove the nagging question of the effect of  r 

o

   

on the important parameters of a transistor configuration.  

  

Z 

i

     

 

 

   Z

b

= br

e

+ c

(

b + 1) + R

C

>r

o

1

+ (R

C

+ R

E

)

>r

o

d R

E

  

(5.25)

    

 Because the ratio    R

C

>r

o

    is always much less than    (

b + 1),    

 

   Z

b

⬵ br

e

+

(

b + 1)R

E

1

+ (R

C

+ R

E

)

>r

o

   

 For     r

o

Ú 10(R

C

+ R

E

),    

 

   Z

b

⬵ br

e

+ (b + 1)R

E

   

 which compares directly with Eq. (5.17). 

 In other words, if    r

o

Ú 10(R

C

+ R

E

),    all the equations derived earlier result. Because 

   

b + 1 ⬵ b,    the following equation is an excellent one for most applications: 

 

   Z

b

⬵ b(r

e

+ R

E

)

  

r

o

Ú10(R

C

+R

E

)

  

(5.26)

     

  

Z 

o

     

 

 

   Z

o

= R

C

储

£

r

o

+

b(r

o

+ r

e

)

1

+

br

e

R

E

§

     

(5.27)

    

 However,     r

o

W r

e

,     and 

 

   Z

o

⬵ R

C

储 r

o

£

1

+

b

1

+

br

e

R

E

§

   

 which can be written as 

 

   Z

o

⬵ R

C

储 r

o

£

1

+

1

1

b

+

r

e

R

E

§

   

 Typically     1

>b     and     r

e

>R

E

    are less than one with a sum usually less than one. The result 

is a multiplying factor for  r 

o

   greater than one. For 

b = 100,     r

e

= 10 ,     and     R

E

= 1 k,    

 

   

1

1

b

+

r

e

R

E

=

1

1

100

+

10 

1000 

=

1

0.02

= 50   

 and  

   Z

o

= R

C

7

51r

o

   

 which is certainly simply  R 

C

  .  Therefore, 

 

   Z

o

⬵ R

C  

Any level of r

o

  

(5.28)    

 which was obtained earlier.  

BJT AC ANALYSIS

270

 

  

A 

v

     

 

 

   A

v

=

V

o

V

i

=

-

bR

C

Z

b

c 1 +

r

e

r

o

d +

R

C

r

o

1

+

R

C

r

o

  

(5.29)

    

 The  ratio     

r

e

r

o

V 1,     and 

 

   A

v

=

V

o

V

i

⬵

-

bR

C

Z

b

+

R

C

r

o

1

+

R

C

r

o

   

 For     r

o

Ú 10R

C

,    

 

   A

v

=

V

o

V

i

⬵ -

bR

C

Z

b

  

r

o

Ú10R

C

  

(5.30)    

 as  obtained  earlier.   

  Bypassed 

 If   R 

E

   of  Fig.   5.29    is bypassed by an emitter capacitor  C 

E

  , the complete  r 

e

   equivalent model 

can be substituted, resulting in the same equivalent network as  Fig.   5.22   . Equations (5.5) 
to (5.10) are therefore applicable. 

  

EXAMPLE 5.3 

  For  the  network  of   Fig.    5.32   ,  without   C 

E

   (unbypassed), determine: 

    a.     r 

e

  .  

   b.     Z 

i

  .  

   c.     Z 

o

  .  

   d.     A 

v

  .   

 

470 k

Ω

C

2  

= 120, r

o

 

= 40 kΩ

β

20 V

2.2 k

Ω

0.56 k

Ω

I

i  

10    F

 μ   

V

i

C

E

C

1

V

o  

Z

i  

Z

o

I

o

10    F

 μ   

10    F

 μ   

 FIG. 5.32 

         Example    5.3   .    

  

Solution:  

 

 

     a.    DC: 

 

    I

B

=

V

CC

- V

BE

R

B

+ (b + 1)R

E

=

20 V

- 0.7 V

470 k

 + (121)0.56 k

= 35.89 mA

 

 I

E

= (b + 1)I

B

= (121)(35.89 mA) = 4.34 mA

   

  

and  

    r

e

=

26 mV

I

E

=

26 mV

4.34 mA

= 5.99 ⍀

    

271

CE EMITTER-BIAS 

CONFIGURATION

    b.    Testing  the  condition     r

o

Ú 10(R

C

+ R

E

),     we  obtain 

 

    40 k

 Ú 10(2.2 k + 0.56 k)

  

40 k

 Ú 10(2.76 k) = 27.6 k (satisfied)   

   

Therefore, 

 

    Z

b

⬵ b(r

e

+ R

E

)

= 120(5.99  + 560 )

 

 

= 67.92 k

   

 and  

    Z

i

= R

B

7

Z

b

= 470 k

7

67.92 k

 

 

= 59.34 k⍀

    

   c.        Z

o

= R

C

= 2.2 k⍀

     

   d.        r

o

Ú 10R

C

     is  satisfied.  Therefore, 

        A

v

=

V

o

V

i

⬵ -

bR

C

Z

b

= -

(120)(2.2 k

)

67.92 k

   

 

= ⴚ3.89

   

   

compared 

to 

-3.93 using Eq. (5.20):    A

v

⬵ -R

C

>R

E

.        

  

EXAMPLE 5.4 

  Repeat  the  analysis  of   Example    5.3     with   C 

E

   in place. 

  

Solution:  

 

 

    a.    The dc analysis is the same, and    r

e

= 5.99 .     

   b.     R 

E

   is “shorted out” by  C 

E

   for the ac analysis. Therefore, 

 

    Z

i

= R

B

7

Z

b

= R

B

7

br

e

= 470 k

7

(120)(5.99 

)

 

 

= 470 k

7

718.8 

 ⬵ 717.70 ⍀

    

   c.       Z

o

= R

C

= 2.2 k⍀     

   d.        A

v

= -

R

C

r

e

    

         

= -

2.2 k

5.99 

= ⴚ367.28 (a significant increase)       

  

EXAMPLE 5.5 

  For  the  network  of   Fig.    5.33     (with   C 

E

   unconnected), determine (using 

appropriate approximations): 

    a.     r 

e

  .  

   b.     Z 

i

  .  

   c.     Z 

o

  .  

   d.     A 

v

  .   

 

C

2  

2.2 k

Ω

C

E  

Z

o 

0.68 k

Ω

16 V

= 210, r

o

 

= 50 kΩ

β

10  k

Ω

90   k

Ω

C

1

V

o  

V

i

Z

i  

+

–

I

o

I

i

 FIG. 5.33 

           Example    5.5   .    

BJT AC ANALYSIS

272

 

  

Solution:  

 

 

     a.    Testing     

bR

E

7 10R

2

,    

 

   (210)(0.68 k

) 7 10(10 k)

 142.8 k

 7 100 k (satisfied)   

   

we 

have 

 

   V

B

=

R

2

R

1

+ R

2

 V

CC

=

10 k

90 k

 + 10 k

(16 V)

= 1.6 V

 

 V

E

= V

B

- V

BE

= 1.6 V - 0.7 V = 0.9 V

 

 I

E

=

V

E

R

E

=

0.9 V

0.68 k

= 1.324 mA

 

 r

e

=

26 mV

I

E

=

26 mV

1.324 mA

= 19.64 ⍀

    

   b.    The ac equivalent circuit is provided in  Fig.   5.34   . The resulting configuration is differ-

ent from  Fig.   5.30    only by the fact that now 

 

   R

B

= R = R

1

7

R

2

= 9 k   

 

R'

I

o

2.2 k

Ω

0.68 k

Ω

90 k

Ω

10 k

Ω

V

i

Z

o 

V

o  

+

–

+

–

Z

i  

I

i

 FIG. 5.34 

        The  ac  equivalent  circuit  of   Fig.    5.33   .    

     The testing conditions of    r

o

Ú 10(R

C

+ R

E

)     and     r

o

Ú 10R

C

    are both satisfied. Using 

the appropriate approximations yields 

 

    Z

b

⬵ bR

E

= 142.8 k

 

 Z

i

= R

B

7

Z

b

= 9 k

7

142.8 k

 

 

= 8.47 k⍀

    

   c.       Z

o

= R

C

= 2.2 k⍀     

   d.       A

v

= -

R

C

R

E

= -

2.2 k

0.68 k

= ⴚ3.24        

  

EXAMPLE 5.6 

  Repeat   Example    5.5     with   C 

E

   in place. 

  

Solution:  

 

 

    a.    The dc analysis is the same, and    r

e

= 19.64 ⍀.     

   b.        Z

b

= br

e

= (210)(19.64 ) ⬵ 4.12 k    

        Z

i

= R

B

7

Z

b

= 9 k

7

4.12 k

   

 

= 2.83 k⍀

    

   c.       Z

o

= R

C

= 2.2 k⍀     

   d.       A

v

= -

R

C

r

e

= -

2.2 k

19.64 

= ⴚ112.02 (a significant increase)        

 Another variation of an emitter-bias configuration is shown in  Fig.   5.35   . For the dc 

analysis, the emitter resistance is    R

E

1

+ R

E

2

,    whereas for the ac analysis, the resistor  R 

E

   in 

the equations above is simply    R

E

1

     with     R

E

2

     bypassed  by   C 

E

  . 

 

  

273

EMITTER-FOLLOWER 

CONFIGURATION

   5.8 

 EMITTER-FOLLOWER  CONFIGURATION 

 ● 

 When the output is taken from the emitter terminal of the transistor as shown in  Fig.   5.36   , 
the network is referred to as an  emitter-follower.  The output voltage is always slightly less 
than the input signal due to the drop from base to emitter, but the approximation    A

v

⬵ 1    

is usually a good one. Unlike the collector voltage, the emitter voltage is in phase with the 
signal  V 

i

  . That is, both  V 

o

   and  V 

i

   attain their positive and negative peak values at the same 

time. The fact that  V 

o

   “follows” the magnitude of  V 

i

   with an in-phase relationship accounts 

for the terminology emitter-follower. 

 

R

C

C

2 

R

B

V

CC

C

E

C

1  

Z

o

R

E

1

V

o  

R

E

2

V

i

Z

i  

I

o

I

i

 FIG. 5.35 

        An  emitter-bias  configuration  with  a 

 portion of the emitter-bias resistance 

bypassed in the ac domain.    

R

E

R

B

V

CC

V

o

C

2  

Z

i  

C

1  

V

i  

B

C

E

Z

o

I

o

I

i

 FIG. 5.36 

        Emitter-follower  configuration.    

 The most common emitter-follower configuration appears in  Fig.   5.36   . In fact, because 

the collector is grounded for ac analysis, it is actually a  common-collector   configuration. 
Other variations of  Fig.   5.36    that draw the output off the emitter with    V

o

⬵ V

i

     will  appear 

later in this section. 

 The emitter-follower configuration is frequently used for impedance-matching pur-

poses. It presents a high impedance at the input and a low impedance at the output, which 
is the direct opposite of the standard fixed-bias configuration. The resulting effect is much 
the same as that obtained with a transformer, where a load is matched to the source imped-
ance for maximum power transfer through the system. 

 Substituting the  r 

e

   equivalent circuit into the network of  Fig.   5.36    results in the network 

of   Fig.    5.37   .  The  effect  of   r 

o

   will be examined later in the section. 

 

BJT AC ANALYSIS

274

 

     

Z 

i

     

  The input impedance is determined in the same manner as described in the preceding 

section: 

 

   Z

i

= R

B

7

Z

b

  

(5.31)    

 with  

   Z

b

= br

e

+ (b + 1)R

E

  

(5.32)

    

 or  

   Z

b

⬵ b(r

e

+ R

E

)  

(5.33)

    

 and  

   Z

b

⬵ bR

E   R

E

Wr

e

  

(5.34)     

  

Z 

o

     

  The output impedance is best described by first writing the equation for the current  I 

b

  , 

 

   I

b

=

V

i

Z

b

   

 and then multiplying by    (

b + 1)     to  establish   I 

e

  . That is, 

 

   I

e

= (b + 1)I

b

= (b + 1)

V

i

Z

b

   

 Substituting for  Z 

b

   gives 

 

   I

e

=

(

b + 1)V

i

br

e

+ (b + 1)R

E

   

 or  

   I

e

=

V

i

[

br

e

>(b + 1)] + R

E

   

 but  

   (

b + 1) ⬵ b   

 and  

   

br

e

b + 1

⬵

br

e

b

= r

e

   

 so  that  

   I

e

⬵

V

i

r

e

+ R

E

  

(5.35)    

 If we now construct the network defined by Eq. (5.35), the configuration of  Fig.   5.38    

results. 

 

 To determine  Z 

o

  ,   V 

i

   is set to zero and 

 

   Z

o

= R

E

7

r

e

  

(5.36)    

R

E

R

B 

c

β

(   

+ 1)

I

e 

=

I

b  

e

r

e

β

b

I

i

V

o

I

o

Z

b

–

+

Z

o  

Z

i

I

b 

V

i  

–

+

I

b

β  

 FIG. 5.37 

        Substituting  the  r 

e

  equivalent circuit into the ac 

 equivalent  network  of   Fig.    5.36   .    

R

E

r

e

V

o

V

i  

I

e

Z

o  

–

+

 FIG. 5.38 

        Defining  the  output  impedance  for 

the emitter-follower configuration.    

275

EMITTER-FOLLOWER 

CONFIGURATION

 Because   R 

E

   is typically much greater than  r 

e

  , the following approximation is often applied: 

 

   Z

o

⬵ r

e

  

(5.37)

     

  

A 

v

     

   Figure   5.38    can be used to determine the voltage gain through an application of the 

voltage-divider rule: 

 

   V

o

=

R

E

V

i

R

E

+ r

e

   

 and  

   A

v

=

V

o

V

i

=

R

E

R

E

+ r

e

  

(5.38)    

 Because   R 

E

   is usually much greater than  r 

e

  ,    R

E

+ r

e

⬵ R

E

     and 

 

   A

v

=

V

o

V

i

⬵ 1  

(5.39)

     

  

Phase Relationship    

  As revealed by Eq. (5.38) and earlier discussions of this section,  V 

o

   

and  V 

i

   are in phase for the emitter-follower configuration.  

  

Effect of  r 

o

 

     

     

  

Z 

i  

   

 

 

   Z

b

= br

e

+

(

b + 1)R

E

1

+

R

E

r

o

  

(5.40)

    

 If the condition    r

o

Ú 10R

E

     is  satisfied, 

 

   Z

b

= br

e

+ (b + 1)R

E

   

 which matches earlier conclusions with 

 

   Z

b

⬵ b(r

e

+ R

E

)

  r

o

Ú10R

E

  

(5.41)     

  

Z 

o

     

 

 

   Z

o

= r

o

储 R

E

储

br

e

(

b + 1)

  

(5.42)    

 Using     

b + 1 ⬵ b,     we  obtain 

 

   Z

o

= r

o

7

R

E

7

r

e

   

 and  because     r

o

W r

e

,    

 

   Z

o

⬵ R

E

7

r

e  Any  r

o

  

(5.43)

     

  

A 

v

     

 

 

   A

v

=

(

b + 1)R

E

>Z

b

1

+

R

E

r

o

  

(5.44)

    

 If the condition    r

o

Ú 10R

E

    is satisfied and we use the approximation    

b + 1 ⬵ b,     we  find 

 

   A

v

⬵

bR

E

Z

b

   

BJT AC ANALYSIS

276

 

 But  

   Z

b

⬵ b(r

e

+ R

E

)   

 so  that  

   A

v

⬵

bR

E

b(r

e

+ R

E

)

   

 and  

   A

v

⬵

R

E

r

e

+ R

E

  

r

o

Ú10R

E

  

(5.45)    

  

EXAMPLE 5.7 

  For  the  emitter-follower  network  of   Fig.    5.39   ,  determine: 

    a.     r 

e

  .  

   b.     Z 

i

  .  

   c.     Z 

o

  .  

   d.     A 

v

  .  

   e.    Repeat parts (b) through (d) with    r

o

= 25 k     and  compare  results.   

 

12 V

3.3 k

Ω

= 100, r

o

 

= ∞ Ω

β

220 k

Ω

V

i  

V

o

I

o

Z

i

Z

o  

I

i

10    F

μ 

10    F

μ 

R

B

R

E

 FIG. 5.39 

         Example    5.7   .    

  

Solution:  

 

 

    a.        I

B

=

V

CC

- V

BE

R

B

+ (b + 1)R

E

    

         

=

12 V

- 0.7 V

220 k

 + (101)3.3 k

= 20.42 mA

     I

E

= (b + 1)I

B

   

 

= (101)(20.42 mA) = 2.062 mA

     r

e

=

26 mV

I

E

=

26 mV

2.062 mA

= 12.61 ⍀

    

   b.        Z

b

= br

e

+ (b + 1)R

E

    

         

= (100)(12.61 ) + (101)(3.3 k)

   

 

= 1.261 k + 333.3 k

   

 

= 334.56 k ⬵ bR

E

     Z

i

= R

B

7

Z

b

= 220 k

7

334.56 k

   

 

= 132.72 k⍀    

   c.        Z

o

= R

E

7

r

e

= 3.3 k

7

12.61 

    

         

= 12.56 ⍀ ⬵ r

e

    

   d.        A

v

=

V

o

V

i

=

R

E

R

E

+ r

e

=

3.3 k

3.3 k

 + 12.61 

    

         

= 0.996 @ 1    

277

COMMON-BASE 

CONFIGURATION

    e.    Checking  the  condition     r

o

Ú 10R

E

,     we  have 

 

   25 k

 Ú 10(3.3 k) = 33 k   

     which is  not  satisfied. Therefore, 

 

    Z

b

= br

e

+

(

b + 1)R

E

1

+

R

E

r

o

= (100)(12.61 ) +

(100

+ 1)3.3 k

1

+

3.3 k

25 k

 

 

= 1.261 k + 294.43 k

 

 

= 295.7 k

   

 with  

     Z

i

= R

B

7

Z

b

= 220 k

7

295.7 k

 

 

= 126.15 k⍀ vs. 132.72 k obtained earlier

 

 Z

o

= R

E

7

r

e

= 12.56 ⍀ as obtained earlier

 

 A

v

=

(

b + 1)R

E

>Z

b

c 1 +

R

E

r

o

d

=

(100

+ 1)(3.3 k)>295.7 k

c 1 +

3.3 k

25 k

d

 

= 0.996 @ 1   

     matching  the  earlier  result.     

 In general, therefore, even though the condition    r

o

Ú 10R

E

    is not satisfied, the results 

for  Z 

o

   and  A 

v

   are the same, with  Z 

i

   only slightly less. The results suggest that for most ap-

plications a good approximation for the actual results can be obtained by simply ignoring 
the effects of  r 

o

   for this configuration. 

 The network of  Fig.   5.40    is a variation of the network of  Fig.   5.36   , which employs 

a voltage-divider input section to set the bias conditions. Equations (5.31) to (5.34) are 
changed only by replacing  R 

B

   by     R

 = R

1

7

R

2

.    

 The network of  Fig.   5.41    also provides the input/output characteristics of an emitter-

follower, but includes a collector resistor  R 

C

  . In this case  R 

B

   is again replaced by the parallel 

combination of  R  

1

  and  R  

2

 . The input impedance  Z 

i

   and output impedance  Z 

o

   are unaffected 

by  R 

C

   because it is not reflected into the base or emitter equivalent networks. In fact, the 

only effect of  R 

C

   is to determine the  Q -point of operation.      

V

i  

V

o

R

E

V

CC

C

1  

C

2  

R

1

I

o

Z

i

Z

o  

I

i

R

2

 FIG. 5.40 

        Emitter-follower  configuration  with  a 

voltage-divider biasing arrangement.    

R

C  

V

i  

V

o

R

E

V

CC

C

1  

C

2  

R

1

I

o

Z

i

Z

o  

R

2

 FIG. 5.41 

        Emitter-follower  configuration  with 

a collector resistor R 

C

 .    

   5.9 

 COMMON-BASE  CONFIGURATION 

 ● 

 The common-base configuration is characterized as having a relatively low input and a high 
output impedance and a current gain less than 1. The voltage gain, however, can be quite 
large. The standard configuration appears in  Fig.   5.42   , with the common-base  r 

e

   equivalent 

model substituted in  Fig.   5.43   . The transistor output impedance  r 

o

   is not included for the 

common-base configuration because it is typically in the megohm range and can be ignored 
in parallel with the resistor  R 

C

  .   

     

Z 

i

     

 

 

   Z

i

= R

E

7

r

e

  

(5.46)     

  

Z 

o

     

 

 

   Z

o

= R

C

  

(5.47)

     

  

A 

v

     

 

 

   V

o

= -I

o

R

C

= -(-I

c

)R

C

= aI

e

R

C

   

 with  

   I

e

=

V

i

r

e

   

 so  that  

   V

o

= aa

V

i

r

e

bR

C

   

 and  

   A

v

=

V

o

V

i

=

aR

C

r

e

⬵

R

C

r

e

  

(5.48)

     

  

A 

i

     

  Assuming  that     R

E

W r

e

     yields 

    

I

e

= I

i

   

 and  

   I

o

= -aI

e

= -aI

i

   

 with  

   A

i

=

I

o

I

i

= -a ⬵ -1  

(5.49)

     

  

Phase Relationship    

  The fact that  A 

v

   is a positive number shows that  V 

o

   and  V 

i

   are in 

phase for the common-base configuration.  

  

Effect of  r 

o

 

     

  For the common-base configuration,    r

o

= 1>h

ob

    is typically in the megohm 

range and sufficiently larger than the parallel resistance  R 

C

   to permit the approximation 

   r

o

7

R

C

⬵ R

C

.    

  

EXAMPLE 5.8 

  For  the  network  of   Fig.    5.44   ,  determine: 

    a.     r 

e

  .  

   b.     Z 

i

  .  

   c.     Z 

o

  .  

   d.     A 

v

  .  

   e.     A 

i

  .   

 

E

V

i

R

C  

R

E

V

CC

C

I

o

Z

i

Z

o  

–

+

V

o

–

+

I

i

I

e

I

c

B

EE

V

+

–

+

–

 FIG. 5.42 

        Common-base  configuration.    

Z

o  

V

o

–

+

R

C  

I

o

V

i

–

+

R

E  

e

c

Z

i

I

i

I

e 

 r

e

α

I

e

I

c

 FIG. 5.43 

        Substituting  the  r 

e

  equivalent circuit into the ac equivalent network 

of   Fig.    5.44   .    

I

e

I

⬵

i

Z

o

Z

i

1 k

Ω

2 V

V

o

+

–

10    F

μ

10    F

μ

= 0.98

α

5 k

Ω

8 V

I

o

V

i

I

i

+

–

r

o

 

= 1 M Ω

+

–

+

–

R

E

R

C

 FIG. 5.44 

         Example    5.8   .    

278